Available for Opportunities

Hey, I'm
Sree Sai Pavan

Systems Programmer & Full-Stack Developer

Electronics and Communication Engineering undergrad at IIT Guwahati. Passionate about compilers, high-performance computing in C++, analog/digital circuit design, and crafting intelligent AI integrations with modern web stack interfaces.

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Pittala Sree Sai Pavan
CVM++ Creator
CF Specialist
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Get To Know Me

About Me

My Journey

I am currently pursuing a Bachelor of Technology in Electronics and Communication Engineering at the Indian Institute of Technology, Guwahati. Deeply interested in the intersection of hardware interfaces and core software architecture.

My coding journey revolves around building things from scratch. Whether it is building a zero-dependency C++ bytecode compiler and virtual machine (CVM++), optimizing graph algorithms (MWIS Solver) with custom bitmasks, or architecting persistent multi-session AI systems using LangGraph and vector embeddings, I enjoy tackling complex challenges and writing highly efficient, optimized code.

Get in touch CGPA: 7.13 (IIT Guwahati)

Developer Archetype

Systems & Algorithms
Systems & Compilers
95%
DSA & Optimization
90%
AI Arch & Memory
85%
Full-Stack Dev
80%
Competitive Prog
88%

Relevant Coursework

Core Electronics

Basic Electronics Digital Circuits Circuit Theory Signals & Systems Analog Circuits Control Systems

Mathematics

Linear Algebra Calculus Differential Equations Real Analysis Complex Analysis Probability & Random Processes

Computer Science

Intro to Computing Computing Laboratory

Education

B.Tech. — ECE
Indian Institute of Technology, Guwahati
7.13 CGPA
2024 – Present
Senior Secondary
Telangana Board of Intermediate Education
96.2%
2024
Secondary
Telangana Board of Secondary Education
97%
2022
My Toolbox

Technical Expertise

C / C++
Used In:
MWIS Solver, CVM++, Automated Circuit Analyser

Low-level memory optimization, DFS branch-and-bound searches, and custom syntax compilers.

Python
Used In:
Automated Circuit Analyser, MWIS tests, AI scripts

Linear system solvers, analytical Laplace solvers, matrix calculations, and NetworkX modeling.

React
Used In:
HabitFlow dashboard, Portfolio UI

Stateful SPA architectures, user flow interactions, custom hooks, and dynamic lists.

HTML / CSS / JavaScript
Used In:
All web interfaces, Terminal shell simulator

Responsive layouts, keyframe animations, dark/light theme toggles, and DOM controllers.

Node.js / Express
Used In:
Portfolio backend, Admin panel

REST APIs, contact route handshakes, and JSON data file read/writes.

NumPy & Pandas
Used In:
Automated Circuit Analyser

Vectorized array math, CSV data ingestion, and scientific matrix solvers.

NetworkX & Matplotlib
Used In:
Automated Circuit Analyser

Circuit graph modeling, adjacency matrices, and transient response plotting.

Git & GitHub
Used In:
All code repositories

Trunk-based branch merges, pull request reviews, and Actions CI/CD workflows.

SymPy
Used In:
Automated Circuit Analyser

Symbolic math equations, Laplace variable transforms, and algebraic impedance solving.

Verilog HDL
Used In:
Traffic Signal Controller (FPGA)

State machine behavioral RTL, synthesis, Vivado deployments, and simulation verification.

LTspice & MATLAB
Used In:
Miller-Compensated OTA design

TSMC 180nm OTA simulations, frequency phase-margin sweeps, and stability compensation checks.

Showcase

Featured Projects

Systems
LEXER → PARSER COMPILER → VM

CVM++ — Stack-Based VM & Compiler

C++17 lexer, parser, bytecode compiler, and virtual machine pipeline executing a custom 23-opcode stack ISA with zero external dependencies.

C++17 Compilers VM System Design
Systems
Git VCS

GitLite — Version Control System

Fully functional version control system in C++17 utilizing SHA-256 content-addressable storage, symbolic HEAD refs, and a DP dynamic programming line-diff solver.

C++17 SHA-256 Dynamic Prog VCS DAG
Algorithms

MWIS Solver — Graph Solver

High-performance C++ solver utilizing branch-and-bound DFS, bitmasks for O(1) checks, and metaheuristic searches on graphs up to 200,000 nodes.

C++17 Graph Theory DFS Bounds Bitmasks
Computational EE

Automated Circuit Analyser

Python circuit solver using NetworkX graph modeling for KCL/KVL, automatic CutSet matrices, and SymPy Laplace s-domain transient responses.

Python NetworkX SymPy Matplotlib
Analog Design

Miller-Compensated OTA

Two-stage OTA designed in TSMC 0.18µm CMOS achieving 71dB DC gain and 14MHz GBW, sized via gm/ID methodology in LTspice.

LTspice CMOS Analog IC gm/ID sizing
Digital Design

Traffic Signal Controller — FPGA

Synchronous 2-state traffic control state machine in Verilog HDL, synthesized and validated on Zedboard (Zynq-7000) FPGA.

Verilog FPGA RTL Zynq-7000 FSM Design
Web Application
Team Portal

Hackathon Squad Dashboard

Interactive React registration dashboard and team board built to coordinate hacker team signups and project entries.

React CSS Variables LocalState Team Board
Web Application

HabitFlow — Habit Tracker

Interactive React application tracking routine streak milestones and rendering SVG-based calendar analytics.

React CSS Variables LocalStorage SVG Analytics
Interactive Playground

Developer Console

ssp_09@iitg-ece: ~
ssp_09@iitg-ece:~$
My Milestones

Timeline & Roles

Oct 2025 – Present IIT Guwahati

Junior Web Developer

Students' Web Committee

Developing responsive, reliable frontend applications and modules for academic, cultural, and community activities at IIT Guwahati. Working on modern JS/React workflows and optimization.

Nov 2024 – Feb 2025 IIT Guwahati

PR & Branding Associate

Alcheringa Fest

Collaborated with core marketing systems to structure outreach materials, manage social media profiles, and boost public branding for Alcheringa—the largest student cultural fest in Northeast India.

Jan 2026 – Present IIT Guwahati

NSS Cell Volunteer

National Service Scheme

Completed 30+ hours of community service and outdoor outreach activities, building organizational systems and driving active volunteer communication.

2024 – Present IIT Guwahati

B.Tech. ECE Undergrad

Indian Institute of Technology, Guwahati

Learning fundamentals of digital systems, circuit design, signal processing, mathematics, computing structures, and laboratory implementation.

What I've Earned

Key Achievements

Codeforces Specialist

Max Rating: 1404

Active competitive programmer (handle: ssp_09). Ranked 1320th globally in Codeforces Round 1090 (Div. 4) and 1994th in Codeforces Round 1083 (Div. 2).

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JEE Advanced 2024

Top 2.53% Nationwide

Ranked in the top 2.53% among over 1.8 Lakh shortlisted candidates across India to secure admission into the Indian Institute of Technology.

TS EAPCET 2024

Top 0.87% State Rank

Ranked in the top 0.87% among 2.4 Lakh competing candidates across the state of Telangana.

Get In Touch

Drop A Message

Contact Information

Have an idea, project, or opportunity you'd like to discuss? Send a message and let's build something cool!

Academic Email p.pittala@iitg.ac.in
Location IIT Guwahati, Assam, India

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